1. Field of the Invention
The present invention relates to an analog semiconductor memory such as an analog audio flash memory and, more particularly, to a redundant analog semiconductor memory circuit in which bad sectors are replaced with redundant sectors.
2. Description of the Related Art
As shown in FIGS. 1A and 1B, an analog audio flash memory comprises an input pad 1, an input amplifier 2, an input low-pass filter (LPF) 3, a write gate voltage generating circuit 4 (known also as a programming voltage generating circuit, referred to below as a VPP circuit), a memory circuit 13 including an address decoder 5 and a memory cell section 6, a shift voltage generating circuit (VSFT circuit) 7, a sense amplifier circuit (SA-AMP circuit) 8, a read gate voltage generating circuit 9 (known also as a verify voltage generating circuit, referred to below as a VVFY circuit), an analog output circuit 10 (known also as a shifted playback output circuit, referred to below as an SHPLYO circuit), an output low-pass filter (LPF) 11, and an output pad 12. The elements in FIG. 1A pertain to the recording process (the writing or programming of the audio signal into the memory); the elements in FIG. 1B pertain to the playback or reproduction process (the reading of the recorded audio signal from the memory).
In the recording process, an analog input voltage AIN1 representing an analog audio signal is received at the input pad 1 and supplied to the non-inverting input terminal of the input amplifier 2. An internally generated analog signal reference potential SG is supplied to the inverting input terminal of the input amplifier 2. The input amplifier 2 subtracts the analog signal reference potential SG from the input audio signal voltage AIN1 to generate an input audio signal voltage AIN, which is supplied to the input low-pass filter 3. This low-pass filter 3 rejects noise components and harmonics present in the input audio signal voltage AIN, and supplies the resulting filtered signal to the VPP circuit 4.
The VSFT circuit 7 generates an analog input shift voltage VSFT1, which is supplied to the VPP circuit 4. The purpose of the analog input shift voltage VSFT1 is to shift the input audio signal voltage AIN upward to a voltage suitable for programming memory cells. The shifting is carried out by the VPP circuit 4, which thereby generates a programming voltage VPP, referred to below as a write gate voltage, responsive to the input audio signal voltage AIN. The write gate voltage VPP is supplied to the address decoder 5 and applied to memory cells in the memory cell section 6. More specifically, the address decoder 5 writes the audio signal in the memory cell section 6 by sequentially selecting the memory cells in the memory cell section 6 and applying the write gate voltage VPP to the gate electrodes of transistors in the selected memory cells.
Referring to FIG. 1B, when the signal is reproduced, the VVFY circuit 9 generates a variable verify voltage VVFY, referred to below as a read gate voltage. The address decoder 5 sequentially selects the memory cells in the memory cell section 6, applies the read gate voltage VVFY to the gates of transistors in the selected memory cells, and outputs the signal read from each memory cell (the memory cell signal ICELL) to the sense amplifier (SA-AMP) circuit 8. The sense amplifier circuit 8 converts the memory cell signal ICELL to a sense amplifier output signal SAOUT which goes either high or low. The VVFY circuit 9 varies the read gate voltage VVFY while monitoring the sense amplifier output signal SAOUT, and finds the VVFY value at which SAOUT switches between high and low; this value is the threshold voltage of the memory cell being read. The VSFT circuit 7 generates an analog output shift voltage VSFT2, which is similar to the analog input shift voltage VSFT1 mentioned above but is supplied to the analog output (SHPLYO) circuit 10. The purpose of the analog output shift voltage VSFT2 is to shift the read gate voltage VVFY down to a value equivalent to the original input audio signal voltage AIN. When the read gate voltage VVFY has settled at the memory cell threshold value, the SHPLYO circuit 10 samples the VVFY value, shifts the sampled value down according to the analog output shift voltage VSFT2, thereby generates an output analog signal SHPLYO equivalent to the original input audio signal voltage AIN, and outputs SHPLYO to the output low-pass filter 11. This low-pass filter 11 rejects noise components and harmonic components present in the output analog signal SHPLYO, and outputs the filtered signal to the output pad 12.
An analog audio flash memory is a type of multi-level memory, in that each memory cell stores a value that can range over many different levels. In the present case, the analog voltage of the audio signal is sampled periodically, and each sample is written as an analog value into one memory cell, as the threshold voltage of a transistor in the memory cell. When the signal is reproduced, the stored values (threshold voltages) are read out as analog values. Accordingly, more information can be stored per memory cell than in a digital flash memory, in which each memory cell stores only a single bit of information (0 or 1). Moreover, the need for analog-to-digital and digital-to-analog conversion is eliminated.
To lengthen the recording and playback times of audio flash memory chips, memory capacities are being increased, necessitating fabrication processes with increasingly smaller feature sizes, and reduced yields due to defective memory cells have become a problem. To keep yields from declining, it has become common to incorporate a redundancy replacement function into the memory circuit 13, by providing redundant memory cells.
FIG. 46 shows the overall layout of a conventional redundant memory circuit comprising a predecoder PDEC and four memory units UMEU0, UMEU1, UMEU2, UMEU3. The notation UMEU will be used below to denote any one of these four memory units. The memory units include redundant sectors, indicated by hatching.
FIG. 47 shows the layout of a memory unit UMEU in more detail. The memory unit UMEU includes four cell arrays UCLA, (individually denoted UCLA-LU, UCLA-RU, UCLA-LD, UCLA-RD), four word line decoders WLDEC (WLDEC-LU, WLDEC-RU, WLDEC-LD, WLDEC-RD), four bit-line decoders UBLDEC (UBLDEC-LU, UBLDEC-RU, UBLDEC-LD, UBLDEC-RD), and four source line decoders USLDEC (USLDEC-LU, USLDEC-RU, USLDEC-LD, USLDEC-RD).
Each cell array UCLA has its own word line decoder WLDEC, bit line decoder UBLDEC, and source line decoder USLDEC. The memory cell section 6 in FIGS. 1A and 1B comprises sixteen cell arrays. The address decoder 5 in FIGS. 1A and 1B comprises the predecoder, the sixteen word line decoders, the sixteen bit line decoders, and the sixteen source line decoders.
A cell array UCLA comprises sixty-four sectors SC (SC0, SC1, . . . , SC63) and one redundant sector RSC. The cell array UCLA has two hundred fifty-six word lines WL (WL0, WL1, . . . , WL255), five hundred twelve bit lines BL (BL0, BL1, . . . , BL511), sixty-four source lines SL (SL0, SL1, . . . , SL63), eight redundant bit lines RBL (RBL0, RBL1, . . . , RBL7), and one redundant source line RSL. This cell array UCLA, incidentally is derivable by adding a redundant sector RSC, redundant bit lines RBL0 to RBL7, and a redundant source line RSL to a non-redundant cell array, shown in FIG. 3, which will be described later.
The word lines WL0-WL255 are controlled by the word line decoder WLDEC, the bit lines BL0-BL511 and RBL0-RBL7 by the bit line decoder UBLDEC, and the source lines SL0-SL63 and RSL by the source line decoder USLDEC.
Each sector SC (and the redundant sector RSC) is a two-kilocell array comprising two thousand forty-eight memory cells. (A kilocell is 210 memory cells.) A cell array UCLA is a 128-kilocell array with an additional two-kilocell redundant sector comprising redundant memory cells. A memory unit UMEU thus has a (512+8)-kilocell configuration.
FIG. 4 illustrates the k-th sector SC less than k greater than  (where k is any integer from 0 to 63) in FIG. 47. The two thousand forty-eight memory cells (one of which is labeled MOL in the drawing) are located at the intersections of the two hundred fifty-six word lines WL0-WL255 and eight bit lines BL less than 8k greater than , BL less than 8k+1 greater than , . . . , BL less than 8k+7 greater than . All of the memory cells in the k-th sector are connected to one source line SL less than k greater than .
FIG. 48 illustrates the redundant sector RSC in FIG. 47. The two thousand forty-eight redundant memory cells (one of which is labeled RMCL) are located at the intersections of the two hundred fifty-six word lines WL0-WL255 and the eight redundant bit lines RBL0 to RBL7. All of the redundant memory cells are connected to the redundant source line RSL. A redundant memory cell RMCL includes a non-volatile memory transistor MTr and an n-channel metal-oxide-semiconductor (NMOS) transistor NTr. The memory cells MCL in FIG. 4 have the same structure.
The predecoder PDEC controls the word line decoders WLDEC, the bit line decoders UBLDEC, and the source line decoders USLDEC, and selects the cell arrays UCLA sequentially when an audio signal is recorded or reproduced (when data are erased and written, or read).
A word line decoder functions as a word line selector. FIG. 5 shows the circuit configuration of the left word line decoders WLDEC-LU and WLDEC-LD; FIG. 6 shows the circuit configuration of the right word line decoders WLDEC-RU and WLDEC-RD. The word lines WL0-WL255 are selected one by one according to row addresses Add0, ADD1, . . . , ADD31 and word line selection signals SXH0, SXH1, . . . , SXH7, SXHB0, SXHB1, . . . , SXHB7. For recording, the write gate voltage VPP is supplied to the selected word line. For reproduction, the read gate voltage VVFY is supplied to the selected word line WL. A more detailed description will be deferred until later.
FIG. 49 shows an example of the circuit configuration of the conventional bit line decoder UBLDEC, comprising NMOS transistors NYB0, . . . , NYB7, NYB504, NYB511, RNYB0, RNYB1, . . . , RNYB7, further NMOS transistors NYA0, NYA1, NYA62, NYA63, RNYA, and still further NMOS transistors NYC0, NYC1, . . . , NYC62, NYC63. This bit line decoder UBLDEC is derivable by adding NMOS transistors RNYB0-RNYB7 and RNYA to a bit line decoder BLDEC for a non-redundant memory circuit, shown in FIG. 7 and described later, in order to select the redundant bit lines RBL0-RBL7.
When data are written or read, the bit line decoder UBLDEC selects the bit lines BL0, . . . , BL7, . . . , BL504, . . . , BL511 and redundant bit lines RBL0-RBL7 (if redundancy replacement has been performed) in sequence, one at a time, according to bit line selection signals YB0, YB1, . . . , YB7, sector selection signals YA0, YA1, . . . , YA7, YC0, YC1, . . . , YC7, and a redundant sector selection signal RYA. When data are written, a memory cell write voltage VW is supplied to the selected bit line BL or redundant bit line RBL. For data reproduction, the memory cell signal ICELL is output on the selected bit line BL or redundant bit line RBL.
FIG. 50 shows an example of the circuit configuration of the conventional source line decoder USLDEC, comprising NMOS transistors NYAB0, NYAB1, . . . ., NYAB62, NYAB63, RNYAB, and further NMOS transistors NYOB0, NYOB1, . . . , NYCB62, NYCB63. This source line decoder USLDEC is derivable by adding one NMOS transistor RNYAB to a source line decoder SLDEC for a non-redundant memory circuit, shown in FIG. 8 and described later, in order to select the redundant source line RSL.
When data are erased, the source line decoder USLDEC selects the source lines SL0-SL63 and redundant source line RSL (if redundancy replacement has been performed) in sequence, one at a time, according to source line selection signals YAB0, YAB1, . . . , YAB7, YCB0, YCB1, . . . , YCB7, and a redundant sector selection signal RYAB. A memory cell erase voltage VERASE is supplied to the selected source line SL or redundant source line RSL.
In the conventional redundant memory circuit, the predecoder PDEC is disposed at one end of the memory units UMEU (adjacent the top memory unit UMEU0 as in FIG. 46). The memory cell section 6 is divided into a left part including eight left cell arrays UCLA-L (UCLA-LU or UCLA-LD) and a right part including eight right cell arrays UCLA-R (UCLA-RU or UCLA-RD). Each part has a capacity of one megacell, giving the memory cell section 6 a capacity of two megacells. Each cell array UCLA has a capacity of 130 kilocells, of which 128 kilocells are memory cells MCL and 2 kilocells are redundant memory cells RMCL.
The word line decoders WLDEC in each memory unit UMEU are disposed between the left cell arrays UCLA-L and the right cell arrays UCLA-R. The bit line decoders BLDEC and source line decoders SLDEC are disposed between the upper and lower left cell arrays UCLA-LU and UCLA-LD, and between the upper and lower right cell arrays UCLA-RU and UCLA-RD.
In the conventional redundant memory circuit, one redundant sector RSC is disposed at the end of each cell array UCLA adjacent the word line decoder WLDEC, as shown in FIG. 47. The redundant sector RSC is thus disposed at the right end of a left cell array UCLA-L, and at the left end of a right cell array UCLA-R.
The sectors SC in each cell array UCLA-LU, UCLA-LD, UCLA-RU, UCLA-RD in FIG. 47 are numbered (from 0 to 63) in their order of access. The word lines WL (0-255), bit lines BL (0-511), and source lines SL (0-63) are numbered in their order of selection. The redundant bit lines RBL are numbered (from 0 to 7) in their order of selection when the redundant sector RSC is used to replace a bad sector.
In the upper cell arrays UCLA-LU and UCLA-RU in the memory unit UMEU in FIG. 47, sectors SC0 to SC63 are accessed, and thus numbered, starting from the end opposite the word line decoder WLDEC; that is, they are numbered from left to right in cell array UCLA-LU, and from right to left in cell array UCLA-RU, with the redundant sector RSC following sector SC63 in each case. In the lower cell arrays UCLA-LD and UCLA-RD, sectors SC0 to SC63 are accessed and numbered starting from the end adjacent the word line decoder WLDEC: from right to left in cell array UCLA-LD, and from left to right in cell array UCLA-RD, with the redundant sector RSC preceding sector SC0 in each case.
Similarly, in the upper cell arrays UCLA-LU and UCLA-RU in the memory unit UMEU, the bit lines BL0-BL511 and redundant bit lines RBL0-RBL7, and the source lines SL0-SL63 and redundant source line RSL, are numbered starting from the end opposite the word line decoder WLDEC; that is, they are numbered from left to right in cell array UCLA-LU, and from right to left in cell array UCLA-RU, the redundant bit lines and source line coming last in each sequence (e.g., RBL0 follows BL511). In the lower cell arrays UCLA-LD and UCLA-RD, the bit lines BL0-BL511 and redundant bit lines RBL0-RBL7, and the source lines SL0-SL63 and redundant source line RSL, are numbered starting from the end adjacent the word line decoder WLDEC: from right to left in cell array UCLA-LD, and from left to right in cell array UCLA-RD, the redundant bit lines and source line coming first in each sequence (e.g., BL0 follows RBL7).
The word lines WL0-WL255 in a cell array UCLA are numbered in sequence starting from the side adjacent the bit line decoder BLDEC. In the upper cell arrays UCLA-LU and UCLA-RU in the memory unit UMEU, accordingly, word lines WL0-WL255 are numbered in sequence from bottom to top; in the lower cell arrays UCLA-LD and UCLA-RD in the memory unit UMEU, word lines WL0-WL255 are numbered in sequence from top to bottom.
First, with reference to memory cell A in FIG. 9, when data are written in a memory cell, the word line decoder WLDEC applies a write gate voltage VPP to the word line WL, thus to the gate of the memory transistor MTr, and the bit line decoder BLDEC applies a memory cell write voltage VW to the bit line BL, thus to the drain electrode of the memory transistor memory transistor MTr. The NMOS transistor NTr is switched on, grounding the source electrode of the memory transistor MTr. This operation injects an amount of charge responsive to the write gate voltage VPP into the floating gate of the memory transistor memory transistor MTr, the threshold voltage of which assumes a value responsive to the write gate voltage VPP.
With reference to memory cell B in FIG. 9, when data are read from a memory cell, the word line decoder WLDEC applies a read gate voltage VVFY to the word line WL. The NMOS transistor NTr is switched on, grounding the source electrode of the memory transistor MTr. The bit line decoder BLDEC and predecoder PDEC couple the bit line BL to the sense amplifier circuit 8. The VVFY circuit 9 monitors the voltage SAOUT output by the sense amplifier circuit 8, and adjusts the read gate voltage VVFY until it is substantially equal to the threshold voltage of the memory transistor MTr.
With reference to memory cell C in FIG. 9, when the data in memory cell MCL are erased, the word line decoder WLDEC grounds the word line WL, the bit line decoder BLDEC opens (disconnects) the bit line BL, and the NMOS transistor NTr is switched off. The source line decoder SLDEC applies a memory cell erase voltage VERASE to the source line SL, thus to the source electrode of the memory transistor MTr. This operation draws charge out of the floating gate of the memory transistor MTr, returning its threshold voltage to substantially the initial value prior to writing.
The procedures for writing, reading, and erasing a redundant memory cell RMCL are the same as the above.
In continuous recording, for example, an audio signal may be recorded in all four memory units, which are accessed in the sequence UMEU0, UMEU1, UMEU2, UMEU3. The signal is then reproduced by accessing the memory units in the same sequence UMEU0, UMEU1, UMEU2, UMEU3. The arrows and circled numbers in FIG. 51 indicate the order in which the memory cells in each memory unit UMEU are accessed during continuous recording and reproduction. First the upper cell arrays UCLA-LU and UCLA-RU are accessed; then the lower cell arrays UCLA-LD and UCLA-RD are accessed.
To record an audio signal, first sector SC0 in the upper left cell array UCLA-LU is erased. Next, the audio signal is written into sector SC0 in this cell array UCLA-LU while the first sector SC0 in the upper right cell array UCLA-RU is being erased. The audio signal is then written into sector SC0 in the upper right cell array UCLA-RU while sector SC1 in the upper left cell array UCLA-LU is being erased. Next, the audio signal is written into sector SC1 in the upper left cell array UCLA-LU while sector SC1 in the upper right cell array UCLA-RU is being erased.
When the signal is reproduced, it is read first from sector SC0 in the upper left cell array UCLA-LU, then from sector SC0 in the upper right cell array UCLA-RU, then from sector SC1 in the upper left cell array UCLA-LU.
Accordingly, the order of sector access in the upper cell arrays is first SC0 in UCLA-LU, then SC0 in UCLA-RU, SC1 in UCLA-LU, SC1 in UCLA-RU, SC2 in UCLA-LU, and so on, concluding with SC63 in UCLA-LU, then SC63 in UCLA-RU. Following access to sector SC63 in UCLA-RU, access shifts to the lower cell arrays, which are accessed in a similar sequence: SC0 in UCLA-LD, SC0 in UCLA-RD, SC1 in UCLA-LD, SC1 in UCLA-RD, SC2 in UCLA-LD, . . . , SC63 in UCLA-LD, SC63 in UCLA-RD. Following access to sector SC63 in UCLA-RD, access shifts to the next memory unit (UMEU), which is accessed in the same sequence as above.
When sector SC0 in cell array UCLA-LU is erased, all of the word lines WL0-WL255 are grounded by turning on transistors NMD0-NMD31 (all at once) and switches SW0-SW255 (all at once or sequentially) in word line decoder WLDEC-LU (see FIG. 5). The bit lines BL0-BL7 in sector SC0 are all disconnected by turning off transistors NYB0-NYB7 in bit line decoder UBLDEC-LU (UBLDEC) in FIG. 49. The memory cell erase voltage VERASE is supplied to the source line SL0 of sector SC0 by turning on transistors NYAB0 and NYCB0 in the source line decoder USLDEC-LU (USLDEC) in FIG. 50. All of the memory cells (e.g., MOL in FIG. 4) in sector SC0 in cell array UCLA-LU are thereby erased.
When the audio signal is written in sector SC0 of cell array UCLA-LU, in word line decoder WLDEC-LU (FIG. 5), transistors PMB0-PMB31 are all turned on at once, If transistors PMA0-PMA31 are turned on sequentially, and switches SW0-SW255 are turned on sequentially. The word lines WL0-WL255 are thereby selected sequentially, one at a time, and the write gate voltage VPP is supplied to the selected word line. In bit line decoder UBLDEC-LU (UBLDEC) (FIG. 49), transistors NYA0 and NYC0 are both turned on and transistors NYB0-NYB7 are turned on sequentially. Bit lines BL0-BL7 are thereby selected sequentially, one at a time, and the memory cell write voltage VW is supplied to the selected bit line. The operation of selecting bit lines BL0-BL7 sequentially is repeated each time a new word line is selected. In each memory cell MCL (FIG. 48) in sector SC0, transistor NTr is turned on, grounding the source electrode of the memory transistor MTr. The memory cells in sector SC0 are thereby selected sequentially, one by one, and the memory transistor MTr in the selected memory cell is programmed by the voltage VPP applied to its gate electrode and the voltage VW applied to its drain electrode, which alter the threshold voltage of the transistor to a value responsive to VPP, thus to the audio signal voltage.
When the recorded audio signal is read from sector SC0 in cell array UCLA-LU, in word line decoder WLDEC-L (FIG. 5), transistors NMB0-NMB31 are all turned on at once, transistors NMA0-NMA31 are turned on sequentially, and switches SW0-SW255 are turned on sequentially. The word lines WL0-WL255 are thereby selected sequentially, one at a time, and the read gate voltage VVFY is supplied to the selected word line. In bit line decoder UBLDEC-LU (UBLDEC) (FIG. 49), transistors NYA0 and NYC0 are both turned on and transistors NYB0-NYB7 are turned on sequentially. Bit lines BL0-BL7 are thereby selected sequentially, one at a time, and the memory cell read signal ICELL is output onto the selected bit line (see BL(ICELL) in FIG. 9). The operation of selecting bit lines BL0-BL7 sequentially is repeated each time a new word line is selected. In each memory cell MCL (FIG. 48) in sector SC0, transistor NTr is turned on, grounding the source electrode of the memory transistor MTr. The memory cells in sector SC0 are thereby selected sequentially, one by one, and the memory cell signal ICELL of the selected memory cell is supplied to the sense amplifier circuit 8. The VVFY circuit 9 generates a read gate voltage VVFY that is brought to a value substantially equal to the threshold voltage of the memory transistor MTr in the selected memory cell (thus a value responsive to the audio signal voltage written into the selected memory cell) as described above.
When sector SC0 in the upper right cell array UCLA-RU is erased, written, or read, word line decoder WLDEC-RU, bit line decoder UBLDEC-RU, and source line decoder USLDEC-RU control word lines WL0-WL255, bit lines BL0-BL7, and source line SL0 in the same way as during the erasing, writing, and reading of sector SC0 in the upper left cell array UCLA-LU.
When sector SC1 in cell array UCLA-LU is erased, written, or read, word line decoder WLDEC-LU, bit line decoder UBLDEC-LU, and source line decoder USLDEC-LU control word lines WL0-WL255, bit lines BL8-BL15, and source line SL1 in the same way as during the erasing, writing, and reading of sector SC0 in cell array UCLA-LU.
FIG. 52 illustrates the sector access sequence when a bad sector BSC (sector SC less than k greater than ) in cell array UCLA-LU is replaced by the redundant sector RSC. The address of the bad sector is programmed into a non-volatile memory provided in the address decoder 5. During initialization operations, which will not be described so as to avoid obscuring the invention with unnecessary detail, the address of the bad sector BSC is read into the predecoder PDEC, bit line decoder UBLDEC, and source line decoder USLDEC. Subsequent accesses to the bad sector BSC are then redirected to the redundant sector RSC in the same cell array UCLA, so that in effect the bad sector BSC is replaced by the redundant sector RSC in the same cell array UCLA.
In the left cell array UCLA-LU shown in FIG. 52, sectors SC0 to SC less than kxe2x88x921 greater than  are accessed sequentially; then, at the timing at which the bad sector BSC would be accessed, the redundant sector RSC is accessed instead, followed sequentially by sectors SK less than k+1 greater than  to SC63. As explained above, however, the upper left and upper right cell arrays UCLA-LU and UCLA-RU are accessed alternately, so sector SC less than kxe2x88x921 greater than  in cell array UCLA-RU is accessed between sector SC less than kxe2x88x921 greater than  and the redundant sector RSC in cell array UCLA-LU, and sector SC less than k greater than  in cell array UCLA-RU is accessed between the redundant sector RSC and sector SC less than k+1 greater than  in cell array UCLA-LU.
In the bit line decoder UBLDEC in FIG. 49, at the timing at which transistors NYA less than k greater than  and NYC less than k greater than  would be turned on to select the bad sector BSC, transistor RNYA is turned on instead, selecting the redundant sector RSC. In the source line decoder USLDEC in FIG. 50, at the timing at which transistors NYAB less than k greater than  and NYCB less than k greater than  would be turned on to select the bad sector BSC, transistor RNYAB is turned on instead, selecting the redundant sector RSC.
As explained above, when an audio signal is recorded in an analog (multi-level) audio flash memory, the audio signal is sampled at predetermined intervals to obtain analog voltage values, which are programmed into successive memory cells by altering the threshold voltage of the memory transistor in each memory cell. When the audio signal is reproduced from the memory, analog voltage levels obtained from the memory cells are amplified and output directly (after a level shift). The recording and reproducing processes have a voltage resolution of, for example, twenty millivolts (20 mV). An analog audio flash memory, accordingly, does not require an analog-to-digital converter or a digital-to-analog converter, both of which would be necessary if the audio signal were stored in a digital (bi-level) audio flash memory.
As explained above, when an audio signal is recorded in the analog audio flash memory, a write gate voltage VPP responsive to the analog voltage level of the audio signal is supplied to the memory cells through the word lines WL and applied to the gates of memory transistors, the threshold voltages of which are thereby programmed to levels responsive to the analog value of the audio signal. When the audio signal is reproduced, a read gate voltage VVFY is supplied to the memory cells through the word lines WL and applied to the gates of the memory transistors to read the programmed threshold voltage. The quality of the reproduced audio signal is therefore affected by the parasitic capacitance and parasitic resistance of the word lines between the word line decoder WLDEC and the memory cells MCL.
The parasitic capacitance and parasitic resistance are illustrated in FIG. 53, which shows the memory cells MCL0, MCL1, . . . , MCL511 and redundant memory cells RMCL0, RMCL6, RMCL7 connected to a word line WL. The letter xe2x80x98cxe2x80x99 denotes the parasitic capacitance of the word line between each mutually adjacent pair of memory cells (including the redundant memory cells); the letter xe2x80x98rxe2x80x99 denotes the parasitic resistance of the word line between each such pair of memory cells (including the redundant memory cells). The memory cells and redundant memory cells are assumed to be equally spaced along the word line WL.
The parasitic capacitance and parasitic resistance of the word line between the word line decoder WLDEC and a memory cell MCL increase in proportion to the length of the word line between the word line decoder WLDEC and that memory cell MCL. The total parasitic capacitance and parasitic resistance of the word line are greatest for memory cell MCL0, which is farthest from the word line decoder WLDEC; the parasitic capacitance and parasitic resistance of the word line decrease in sequence from memory cell MCL1 to memory cell MCL511.
As a result of the parasitic capacitance and parasitic resistance, when a word line is selected, the gate voltage of the memory transistors in different memory cells rises (to the write gate voltage VPP or read gate voltage VVFY) at different rates, depending on the location of the memory cells, as shown in FIG. 54. VG1 is the gate voltage of the memory transistor in, for example, memory cell MCL511, which is closest to the word line decoder WLDEC; VG2 is the gate voltage of the memory transistor in, for example, memory cell MCL0, which is farthest from the word line decoder WLDEC. The length of time for which the appropriate voltage (VPP or VVFY) is to be applied to the gate of the memory transistor is denoted T, while TD denotes the delay from the rise of VG1 to the rise of VG2.
The reason for the delay TD is that the parasitic capacitance of the word line WL from the word line decoder WLDEC out to a relatively distant memory cell such as MCL0 is greater than the parasitic capacitance of the word line WL from the word line decoder WLDEC out to a closer memory cell such as MCL511.
FIGS. 55A and 55B show the results of experiments in which memory cells were programmed to a nominal threshold voltage of 6.12 V. FIG. 55A is a histogram of threshold voltages Vt obtained in memory cells close to the word line decoder WLDEC (for example, memory cell MCL511); all of the threshold voltages are within twenty millivolts (xc2x120 mV) of the nominal value. The threshold voltage is indicated in volts on the horizontal axis, and the number of memory cells 0-1400 in which the voltage was obtained is indicated on the vertical axis. FIG. 55B is a histogram of threshold voltages Vt obtained in memory cells far from the word line decoder WLDEC (for example, memory cell MOL0); some of the threshold voltages differ from the nominal value by as much as eighty millivolts (6.12xe2x88x926.04=0.08 V=80 mV).
Differences in the programmed threshold voltage such as the differences between FIG. 55A and FIG. 55B tend in particular to occur when the programming time is shortened in order to increase the operating speed of the memory. Such differences can also occur if fabrication process variations increase the parasitic capacitance and resistance of the word lines. These differences lead to differences in the values read from the memory cells (the read gate voltage VVFY).
A further cause of differences in the programmed threshold voltage is the gate disturb effect, in which the reading or writing of a memory cell disturbs the threshold voltages programmed into other memory cells on the same word line. For example, if data are first written into the memory cells MCL at the end of the word line near the word line decoder WLDEC, the threshold voltages of these memory cells may further increase, altering the stored analog data values, when data are written into the memory cells at the end of the word line distant from the word line decoder WLDEC.
Thus the parasitic capacitance and parasitic resistance of the word lines tends to reduce the programmed threshold voltages of memory cells at the far end of the word line, while the gate disturb effect can raise the programmed threshold voltages of memory cells at the near end of the word line, as seen from the word line decoder WLDEC.
If the programmed voltage of a single memory cell MCL differs by more than twenty millivolts from the intended value, or if the programmed threshold voltages of two memory cells in two different sectors that are accessed consecutively deviate in opposite directions from the intended values and the sum of the absolute values of the deviations exceeds twenty millivolts, a listener may notice a defect in the reproduced audio signal. It is to prevent such audible defects that the memory cells are accessed in the sequence indicated in FIG. 51. Although the programmed threshold voltages differ depending on the distance of the memory cell MCL from the word line decoder WLDEC, if the cells are accessed in the sequence in FIG. 51, the profile of deviations in the programmed threshold voltage will be free of sharp discontinuities, and the audio signal reproduced from the analog audio flash memory will not be noticeably degraded.
In the conventional analog audio flash memory described above, however, the smoothness of the voltage deviation profile is broken if a bad sector BSC distant from the word line decoder WLDEC is replaced with the redundant sector RSC disposed adjacent the word line decoder WLDEC. If the bad sector BSC is sector SC less than k greater than , access jumps from sector SC less than kxe2x88x921 greater than  to the redundant sector RSC, then back to sector SC less than k+1 greater than . This can cause a major discontinuity in the threshold voltage deviation profile, and can degrade the quality of the reproduced audio signal (the reproduced analog signal).
A further problem is that redundancy replacement is limited to one sector per cell array, so if there are two bad sectors in a cell array, they cannot both be replaced with redundant sectors. This problem becomes increasingly severe as the size of the cell arrays is increased, adversely affecting production yields of high-capacity analog audio flash memories.
An object of the present invention is to reduce the adverse effect of redundancy replacement on the quality of the signal reproduced from an analog semiconductor memory.
Another object of the invention is to improve the fidelity of the reproduced signal.
Yet another object is to increase the capability of an analog semiconductor memory for redundancy replacement.
The invention provides a redundant memory circuit for use in an analog semiconductor memory. The redundant memory circuit includes a cell array having a first end and a second end, with a plurality of word lines extending from the first end to the second end and a plurality of memory cells connected to the word lines. Each memory cell stores an analog value. The cell array is divided into a plurality of sectors and includes at least one redundant sector that can be used to replace a bad sector. The redundant memory circuit also includes a word line selector for selecting the word lines.
According to a first aspect of the invention, the cell array includes a pair of redundant sectors, one disposed at the first end and the other disposed at the second end of the cell array. Aside from the redundant sectors, the sectors in the cell array are accessed in sequence from the first end to the second end, or from the second end to the first end. When there is a single bad sector in the cell array, it is replaced by the closer one of the two redundant sectors, and this redundant sector takes the place of the bad sector in the access sequence.
The first aspect of the invention improves the capability for redundancy replacement by providing two redundant sectors per cell array, so that two bad sectors can be replaced. In addition, redundancy replacement of a single bad sector changes the distance to the word line selector by at most half the length of the array, thus reducing the maximum size of any resulting discontinuity in the threshold voltage deviation profile. The adverse effect of the replacement on the quality of the reproduced audio signal is accordingly reduced.
According to a second aspect of the invention, the redundant sector in a cell array is located centrally in the array. This arrangement similarly reduces the adverse effect of redundancy replacement on the quality of the reproduced audio signal, by limiting the change in distance to the word line selector occasioned by the replacement to at most half the length of the array, thus limiting the size of any resulting discontinuity in the threshold voltage deviation profile.
According to a third aspect of the invention, the redundant memory circuit includes a sector selection circuit that selects the sectors and redundant sector in sequence from one end of the cell array to the other, skipping a bad sector if one is present. This arrangement virtually eliminates the discontinuity in the threshold voltage deviation profile caused by redundancy replacement, so the quality of the reproduced audio signal is scarcely affected by the redundancy replacement.
According to a fourth aspect of the invention, the word line selector is located in the center of the cell array. This arrangement not only reduces the adverse effect of redundancy replacement on the reproduced audio signal quality, by limiting the change in distance to the word line selector occasioned by replacement to at most half the length of the array, but also improves the fidelity of the reproduced audio signal, regardless of whether redundancy replacement is carried out or not, by reducing the maximum size of the threshold voltage deviations in the threshold voltage deviation profile.
According to a fifth aspect of the invention, the redundant memory circuit has two cell arrays with respective sectors, redundant sectors, and word line selectors. The redundant memory circuit also includes a redundant sector selection circuit that selects the redundant sectors in both cell arrays, so that a bad sector in one cell array can be replaced by a redundant sector in either of the two cell arrays. The capability for redundancy replacement is thereby improved, because any two bad sectors in the two cell arrays can be replaced, even if the two bad sectors are both situated in the same cell array.